Libre Silicon

Free semiconductors for everyone

We develop a free (as in freedom, not as in free of charge) and open source semiconductor manufacturing process standard, including a full mixed signal PDK, and provide a quick, easy and inexpensive way for manufacturing. No NDAs will be required anywhere to get started, making it possible to build the designs in your basement if you wish so. We are aiming to revolutionize the market by breaking through the monopoly of proprietary closed source manufacturers!

The idea Get more info Getting started

Opening the market

Today there is no inexpensive and easy way for SMEs, startups and hobbyists to develop their own ASICs and bringing them to the market. All the silicon manufacturing nowadays is in the hands of a few big companies which play their monopoly of lone capability of manufacturing microchips by charging around 2'000 USD per prototype and letting an engineer wait for months until she/he can test her/his design physically. Additionally the EDA tools for designing chips are unaffordable for most start ups. We intend to change that!

Auditable chips solving security concerns

Since at least the introduction of the Intel Management Engine and the emergence of Spectre and Meltdown, the concerns about the trustworthiness and security of CPUs in our computers, smartphones and other devices is raising. By providing a fully open process and technology node which allows to publish the entire layout, the doors for entirely free CPU platforms are being pushed open which allow for a full security audit down to the transistor level. Which means increased assurance of security via peer review and no more hidden hardware backdoors for intelligence agencies.

Global reproduciblity

In order to democratize the semiconductor market, a standardized free manufacturing process needs to be introduced in order to easily exchange designs and silicon-verify them anywhere on the globe. By specifying the target parameters of test structures we provide, required for supporting the LibreSilicon technology, it becomes possible to design and test any ASIC (CMOS *and* analog!) somewhere in Tokyo and then download the design from GitHub and manufacture it anywhere else in the world. That's what we're doing.

Leveling the playfield

Today, the field of free and open-source silicon is very uneven. SMEs, individual FOSHW developers and hobbyists have no chance to implement their designs for practical purposes except for FPGAs, with no provision at all for analog, mixed-signal or high-performance, low-power, space-constrainted applications. As for "Open" chips, the privilege of IP integation, "the final pull" is in the hands of their sponsors, barring users from benefiting from the advantages of their FOSHW nature. On the other end of the pipe, Big-tech corporations embracing the "open-source is out-source" paradigm are siphoning the effort of developers for gratis into commercial products. By providing unfettered and viable access to small players to semiconductor manufacturing, we aim to turn "open-source silicon" into true Free and Open-Source LibreSilicon!

Our Vision and Mission

Our vision is a world where the "Silicon Barrier" does not exist. Access to integrated circuit technology is as commonplace as printed circuit board is, and not only for the top corporations. Knowledge of integrated circuit design is the part of the basic skills of an electrical engineer not only because of its relevance, but also because of its everyday usefulness. High-quality FOSS electronic design automation software is available. Process Design Kits, the information needed to design for a particular technology node, are publicly available. GDSII is an everyday counterpart of Gerber files. The paradigm of large-scale integration penetrates the product or project designs of companies, being large or small, SMEs, start-ups, and individual hobbyists and amateurs.

Deciding what and how is made in CPUs and SoCs of computers, smartphones, routers and other everyday computing devices is not a privilege of a few big corporations. The freedoms defined in relation to free software are valid to computer hardware: users are permitted to study, or if one decides so, modify them. Trust towards digital technology is rooted in complete transparency. CPU design is not one-size-fits-all, custom CPUs are commonplace.

Having these custom integrated circuits manufactured is affordable, providing a comparable economic performance over discrete or programmable-logic realization even down to the smallest volumes. The required capability of realization of unique ICs is provided by a new branch of the semiconductor industry: fabs, ranging from garage enterprises to industrial-scale ones, distributed all around the globe, serving local and/or global demand of custom IC fabrication. As for their clients, everyone is invited, even individuals, with no minimum order quantities, nondisclosure agreements or demands of excessive legal paperwork. Ordering a low-volume custom IC run is as easy and straightforward as ordering a PCB. The common denominator between these fabs is a set of open-source technology nodes that provide design portablity.

What needs to be changed ...

One may say, the vision outlined before is the complete opposite of the current situation, and one is right. There are many areas that need to be addressed, from paradigm change and education to the availablity of viable free CPU designs and of semiconductor manufacturing services.

First and foremost, the attitude towards semiconductor industry in general needs a shift: it is impossible to reach the goal as long as no-one believes that IC fabrication can be more accessible than it is today. Also, a paradigm shift is necessary: that designers consider integrated implementation instead of realization using a PCB with catalog components as a viable alternative. Besides that, the specific knowledge and skills on IC design, including analog, digital and system-level aspects, has to be included in education of engineers, both via institutional and autodidactic paths.

In addition to these, breaking the "Silicon Barrier" is not possible without the proper tooling. Design of integrated circuits is a speciality field within electrical engineering, therefore specialized EDA tools are necessary, that have the maturity and quality to be used for practical work. This includes, among others, circuit simulation, layout, DRC, LVS, and parasitic extraction tools, electromigration, signal and power integrity checkers, and many more. Unfortunately, current software implementing these functions are either commercial products with pricetags targeted at big-tech, or open-source software with limited functionality and maturity.

Of course, all of these can work only if there is a rationale to invest effort into them, which mandates the availablity of useful designs and a way to exchange them. One of the most anticipated benefits of LibreSilicon is the transparency, customizablity and trustworthyness of the CPUs and SoCs it provides, that means it is imperative for success that high-quality open-source digital processor core designs exist. Also, specialized applications will need purpose-tailored digital cores, as well as analog blocks and the primitives to form them. Of course, the integration of a digital core into a real chip requires many non-digital components, like bonding pads, ESD protection, oscillators, PLLs, nonvolatile memories, various physical interface circuits and manufacturing-related features.

An important, if not the most important prerequsite of the change is the availablity of a set of free technology nodes on which these designs can be realized. The range and feature set of these nodes needs to be diverse, with deep-submicrometer nodes available for dense digital designs, larger feature-size nodes for mixed-signal and analog circuits, and specialized options for niche applications like power management, high-voltage, RF, and so on. The free and open nature of these nodes is imperative, as it enables the unfettered availablity of PDKs to designers, and allows massive adoption by fabs, which is a prerequsite for design portablity and supply-chain security.

These nodes, however, carry no practical value alone. In order to be useful, it is needed that the nodes are actually being manufactured. In practice, this may be achieved by adoption of the nodes by existing fabs, or by the emergence of new manufacturers tailored for them, or by both. In all cases, the geographically diverse availablity of independent manufacturing vendors is desirable, as it increases the resilience of the supply chain and prevents monopolization, thus enables affordable access via competition. It has to be understood that many FOSHW developers are motivated into developing IP cores to solve real-life problems. Since, as stated before, the availablity of high-quality IP cores is imperative, accessiblity of these services to small customers is an important aspect. Therefore, and for the true provision of user-customizablity of FOSHW designs, it is paramount to find, implement and encourage the adoption of novel business models and behaviors that allow small players to benefit from LibreSilicon. This includes not only a change in the now-current attitude of fabs slamming the door at the customer below one million units, but also a departure from optimizing manufacturing processes to massively large volumes. The latter is also important to ensure that low-volume production is not only accessible, but also affordable. This involves re-thinking of economies of scale, introduction of new ways to organize manufacturing operations, and the development and introduction of novel mask-less lithography technologies, that can meet the resolution and troughput requirements of cost-effective production both at large and small scale.

... and how will we make it happen?

We aim to take an active role in driving forward the change and reaching the objectives outlined before. Considering the fact that the free and open-source silicon ecosystem is growing explosively since the second half of the 2010s, many of the objectives are addressed already by others. In these cases, we want to support their effort and adapt their results, without aiming at realizing the same goal in a different way, thus preventing the fragmentation of the ecosystem. In other topics, however, there is either no progress or the progress is not going in the desirable direction. In these cases, we take a leading role, using the fullest possible extent of our expertise, commitment and resources. Our focus topics, without particular order, are the following:

In addition to these efforts, we also aim at providing valuable contribution in the efforts of others with a shared goal, including:

Standard Cell Library Generator

Standard Cells are the basic building blocks of modern chip-design, they are used to automatically synthesize, place and route digital logic into chips. The synthesis step (e.g. done with yosys) chooses which standard cells should be used to implement the given logic, then the placement step places the cells on a grid, then the routing step connects the standard cells with metal connections for power and signals. At Libresilicon we believe that having many more standard cells will make the overall designs more efficient because the synthesis engine can choose from more cells, therefore we are automating the generation of whole standard cell libraries.


The development of the StdCellLib generator started in 2018, it is currently targeted for LS1U, Sky130 and GF180, and we did successful tapeouts on Sky130 already. We have prepared a library for GF180 for 5V already but haven’t taped it out yet.

Currently not yet in scope: Pad-Cells, but we hope to do that in the future, once the work on the standard cells is finished.

Test Structure Generator

Test Structures are used to create Test-Chips with various carefully designed test structures on them which can then be measured to see and model the actual behavior of the chip production process. This can be used during process development to bring up a new process node, it can also be used to be placed on every wafer for quality assurance during production. It can also be used to additionally characterize an existing process node for new applications like new chemical layers like e.g. Hafnium, …

The initial project was the manually designed Pearl River for 1um process:


Pearl River was actually produced in the lab of HKUST in 2018 (Hong Kong University of Science and Technology) and transistors were tested successfully:





In 2023 we developed the automated successor, called DanubeRiver and taped it out successfully in cooperation with Google on GobalFoundries GF180.


One of our GF180 test structure chips was successfully photographed by Andrew (“Bunnie”) Huang:



LibrePDK is a software library which does parametric generation of structures, based on available design rules. It is used by DanubeRiver to create the teststructures, and it uses gdspy itself for generating GDS-II which is the data format used to transmit the chip design to the semiconductor factory. LibrePDK was developed in 2022/2023 It has been successfully used in the GF180 tapeout for DanubeRiver.

LS1U - Libresilicon 1um Process Node

This is a fully open source, fully documented (process specifications, DRC rules, …) CMOS process design, with the goal that it should be adoptable by university labs and in the long run hobbyists. The tests had started at HKUST, but were interrupted and haven’t been completed yet. Several universities have adopted the process documentation in their lectures to teach CMOS manufacturing, e.g. JKU Linz (Austria). The long term goal is to find alternative chemical recipes, which allow for private hobbyists to make their own chips without having to use very dangerous gasses like Silane, here is a not yet reliably verified alternative recipe for depositing Polysilicon for example: Eco friendly Polysilicon deposition_(CVD)

Our roadmap

The roadmap itself can be found here through the Roadmap Wiki Link


Successful tapeout of the Danube with Global Foundries

12/21/2023: The first successful tapeout of the new autogenerated process verification wafer Danube River

Congress talk at the 35C3

11/14/2018: There will be a 1.5 hour talk about this project at Chaos Communication Congress 35c3.

Lightning talk at the 34c3

12/16/2017: There will be a lightning talk about this project at Chaos Communication Congress 34c3.

Hackathon at the C3D2

Free semiconductors for everyone

From: 2018-05-19 Sat 12h

Until: 2018-05-21 Mon OpenEnd

Zentralwerk Riesaer Str. 32, 01127 Dresden



David Lanzendörfer

Process Design

Studied electrical engineering but realized that there were no interesting jobs to be done in Switzerland. So he ventured out to China in order find his fortune there. In this new world he found all the thrilling engineering problems, he ever wanted to solve, and now tackles the final frontier: Semiconductor manufacturing.

david dot lanzendoerfer at libresilicon dot com


Philipp Gühring

Software Design

Software developer for 25 years. Security and Cryptography enthusiast.

philipp dot guehring at libresilicon dot com


Hagen Sankowski

Digital Design

In business for 20 years, worked for a Samsung subsidiary, later freelancing for Intel Mobile Communication, Infineon Chipcard, Globalfoundries and many others as ASIC Designer.

hsank at posteo dot de


Ferenc Éger

Analog Design

Electrical engineer, currently in the automotive sector. Previously worked at Microchip Technology, and on custom-order system development projects (both HW and SW) since 2010. Studied microelectronics manufacturing and design at Budapest University of Technology.

eegerferenc at gmail dot com

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Open Circuit Design